1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly relates to a technique useful for use in system LSI for mobile device, microprocessor and the like.
2. Description of Related Art
The number of circuit blocks integrated in one LSI is remarkably increased due to progress in fine processing technology of semiconductors, and therefore usually unimaginable, complicated information processing can be achieved in one chip. Such LSI is called SoC (System on a Chip) and used for a system for mobile device and the like. However, a leakage current in a single transistor tends to increase due to progress in fine processing technology of semiconductors. As a result, the total leakage current in SoC is becoming extremely increased.
To such SoC in which a large number of circuit blocks are integrated in one chip, demand on further high-speed operation of the circuit blocks is becoming increased with improvement in functions which is required for mobile devices and the like. For example, even if a transistor that can perform high-speed operation such as a transistor having a low threshold voltage or a transistor having a small thickness of a gate insulating film is used to achieve such high-speed operation, increase in leakage current is inevitable. Therefore, it is an important issue for SoC that increase in leakage current is prevented, in addition, high-speed operation is achieved.
In SoC used for a system for mobile device or the like, the integrated circuit blocks can be exclusively used, and currently, only a necessary circuit is typically operated correspondingly to a scene to be used (hereinafter, simply called mode) or the like. That is, in SoC, an operation period can be definitely distinguished from a non-operation period in the integrated circuit blocks. When such technology is used, an idea is given, that is, circuits are configured by high-speed devices that can be operated at high speed, and power shutdown is closely performed during non-operation period so that the circuits are operated at extremely high speed in the operation period, and the leakage current is reduced in the non-operation period.
JP-A-2004-235470 discloses a control method of power shutdown that can extremely reduce the leakage current by performing control using a switch having a large thickness of a gate insulating layer of transistors. However, since such a switch having the large thickness of the gate insulating layer takes large area, when a large number of power shutdown regions are provided within a chip, areal overhead costs are extremely increased, and therefore the switch is becoming hard to be mounted. On the other hand, when power is shut down using a switch having a small thickness of the gate insulating layer, while increase in area of the power switch can be reduced, an effect of reducing the leakage current cannot be sufficiently obtained compared with a case that power is shut down using the transistor having the large thickness of the gate insulating layer.
JP-A-6-203558 discloses a technique that power shutdown of LSI is hierarchically carried out, thereby a period is reduced, in which a voltage level of a circuit being subjected to power shutdown is unstable, so that time for subsequently returning the circuit to an original state by voltage application is made faster.
In a non-patent document 1, Y. Kanno, et al., “Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor,” ISSCC Dig. Tech. Papers, PP. 540-541, 671, February, 2006; SoC is disclosed, which has a plurality of power domains provided within a chip, power switches (PSW) for the power domains, and SRAM macros arranged in the power domains. Here, the power domain refers to a region where power shutdown can be performed using a power switch, which corresponds to the above power shutdown region. The power switch includes n-channel MOS transistors, each transistor having a large thickness of a gate oxide film and a high threshold voltage, for which transistors used in an external input/output circuit (I/O) are used. In the SRAM macros, special power switches are provided for reducing the leakage current.